Algorithm and Architecture Co-optimization for Digital Enhancements of Deep Submicron CMOS Transceivers

In this work, we identify the new challenges which arise when implementing digital intensive transceivers for multi-mode communications. Multi-mode transceivers require analog front-ends that operate well over a large number of frequency bands, challenging the frequency mixing and increasing the sensitivity to timing and amplitude mismatches. To tackle these new challenges, we bring system architecture together with digital signal processing (DSP) algorithm and architecture design to obtain a better understanding of the key tradeoffs of performance metrics. We carry out the studies for the following three concrete cases. Timing mismatches of parallel mixing paths limits the achievable harmonic rejection (HR) performance in a multi-mode transceiver design. This thesis proposes a digital intensive multi-path mixing architecture and an iterative mismatch calibration method aiming at joint calibration for transmitter (Tx) and receiver (Rx), using on-chip loopback and a dedicated test signal. The proposed architecture and calibration scheme enables high HR performance in presence of substantial timing mismatches. Although a digital intensive multi-path mixing architecture can improve HR performance, it significantly increases design challenges in the radio frequency digital-to-analog converter (RFDAC) blocks in the digital transmitter. This thesis presents a low-cost one-current RFDAC architecture, which migrates the LO mixing operation to the digital domain, and allows to cut the required number of current cells in RFDAC by half at the cost of the increased sensitivity to timing mismatch problem. To enable the one-current RFDAC architecture, an effective predistortion scheme based on a run-time binary-tree descent searching scheme is proposed to tackle the timing mismatch problem in the one-current RFDAC architecture. Finally, an optimized and power-efficient implementation of the proposed timing correction scheme is presented. To also apply the RFDAC architecture for millimeter-wave communication, and tackle the problems in the traditional analog-centric polar transmitter, we propose a new digital-intensive transmitter architecture with polar concept expanded to the whole transmitter. Further, this work optimizes the digital frontend for a polar transmitter working in the 60 GHz band. As a very high bandwidth is available at 60 GHz, a digital frontend operates at very high frequency, which can easily become the bottleneck in the system power budget if not optimized carefully. The systematic optimizations are first explored to minimize the design requirements on the digital frontend. An efficient latchbased pipeline is then studied to provide the required 7.04 Gsps throughput with power consumption of less than 60 mW. The synthesis results compare favorably with previously reported architectures. By exploring a digital intensive multi-path HR mixing architecture, a lowcost one-current RFDAC architecture and an energy efficient digital frontend processor for 60 GHz polar transmtter, this thesis contributes to more energy efficient and high-performance wireless communications systems that can be implemented in the deeply-scaled Silicon technologies.Contents Acknowledgements i Abstract iii Beknopte samenvatting v Abbreviations vii Contents ix List of Figures xiii List of Tables xvii 1 Introduction 1 1.1 Motivations: A Clear Trend to Digital Intensive Solution to Multi-mode Radio . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 Wish for Flexibility in Mobile Radios . . . . . . . . . . 1 1.1.2 Wish for Technology Scaling . . . . . . . . . . . . . . . 3 1.1.3 Clear Trend to Digital Intensive Transceiver . . . . . . . 4 1.2 Digital Intensive Wireless Communication System . . . . . . . 5 1.2.1 Background on Wireless Communication Systems . . . . 5 1.2.2 Multi-mode Digital Transmitter . . . . . . . . . . . . . . 7 1.2.3 Multi-mode Digital Intensive Receiver . . . . . . . . . . 11 1.3 Challenges in the Digital Intensive Radio . . . . . . . . . . . . 13 1.3.1 Harmonic mixing . . . . . . . . . . . . . . . . . . . . . . 13 1.3.2 Amplitude and Timing Mismatch of RFDAC cells . . . 15 1.3.3 High Complexity in Digital Front-end Design . . . . . . 16 1.4 Research Scope and Main Contributions . . . . . . . . . . . . . 18 1.4.1 Research Scope . . . . . . . . . . . . . . . . . . . . . . . 18 1.4.2 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2 Digital Intensive Multi-path Harmonic Rejection Transceiver 23 2.1 Introduction and Related Work . . . . . . . . . . . . . . . . . . 24 2.2 Motivation for Digital Intensive Multi-path Transceiver . . . . 26 2.3 General Mathematical Framework for Multi-path harmonic Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.1 Mathematical Description of Framework . . . . . . . . . 27 2.3.2 Exploration of Optimal Scaling Factors’ Generation . . 31 2.4 Proposed Iterative Timing Calibration to Improve Harmonic Rejection Performance . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.1 Performance Limitations of Analog Recombination and Mixed-signal Compensation method . . . . . . . . . . . 32 2.4.2 Proposed Iterative Calibration Flow . . . . . . . . . . . 35 2.4.3 Proposed Calibration of Two-path Timing Mismatch . . 38 2.4.4 Digital Recombination and Digital Compensation . . . . 43 2.5 Performance of Iterative Calibration Scheme . . . . . . . . . . . 45 2.5.1 Theoretical HR Performance . . . . . . . . . . . . . . . 45 2.5.2 HR Performance under Realistic Non-ideal Scenarios . . 46 2.5.3 HR Performance for Jointly Rejecting Both HIs . . . . . 49 2.6 Conclusion and RFDAC Design Challenges with Multi-path Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.6.2 RFDAC Challenges . . . . . . . . . . . . . . . . . . . . 53 3 One-current RFDAC Architecture for Low-cost Transmitter 55 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.2 Low-cost RFDAC and its Increased Susceptibility to Timing Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.2.1 Non-overlapping I and Q LOs . . . . . . . . . . . . . . . 61 3.2.2 Overlapping I and Q LOs . . . . . . . . . . . . . . . . . 63 3.3 Challenges with Traditional Predistortion Schemes . . . . . . . 65 3.3.1 Importance of the Missing Glitches . . . . . . . . . . . . 65 3.3.2 Challenge in Predistortion with LUT . . . . . . . . . . . 67 3.4 Proposed Binary-tree Descent Searching Scheme to Calibrate Timing Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.5 Simulation Performance and Analysis . . . . . . . . . . . . . . 73 3.6 Architecture Implementation Exploration . . . . . . . . . . . . 75 3.6.1 Initial Implementation . . . . . . . . . . . . . . . . . . . 76 3.6.2 Implementation Optimization . . . . . . . . . . . . . . . 78 3.7 Proposed Switching Sequence to Compensate Gradient Errors in RFDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.7.1 Related Work . . . . . . . . . . . . . . . . . . . . . . . . 83 3.7.2 Proposed Switching Approach . . . . . . . . . . . . . . . 86 3.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4 Energy-efficient Digital Frontend Processor for 60 GHz polar transmitter 91 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.2 Challenges in Traditional Polar Transmitter . . . . . . . . . . . 93 4.3 Proposed Digital Polar Transmitter Architecture . . . . . . . . 94 4.3.1 General Description of the DSP Functionalities . . . . . 95 4.4 Proposed Energy-efficient Digital front-end Processor Design . 100 4.4.1 Optimization of DSP Design Requirements . . . . . . . 100 4.4.2 DFE Architecture Exploration . . . . . . . . . . . . . . 104 4.5 Results and Comparisons . . . . . . . . . . . . . . . . . . . . . 118 4.5.1 Results and Comparisons with Other Polar Conversion Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.5.2 Comparisons of DSP Complexity with that in Outphasing Architecture . . . . . . . . . . . . . . . . . . . . . . . . 118 4.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5 Conclusions and Future Work 123 5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.1.1 Conclusions Regarding Main Contributions . . . . . . . 124 5.1.2 General Conclusions . . . . . . . . . . . . . . . . . . . . 126 5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Bibliography 131 List of publications 145nrpages: 167status: publishe

Advancements in the study of inward rectifying potassium channels on vascular cells

ABSTRACTInward rectifier potassium channels (Kir channels) exist in a variety of cells and are involved in maintaining resting membrane potential and signal transduction in most cells, as well as connecting metabolism and membrane excitability of body cells. It is closely related to normal physiological functions of body and the occurrence and development of some diseases. Although the functional expression of Kir channels and their role in disease have been studied, they have not been fully elucidated. In this paper, the functional expression of Kir channels in vascular endothelial cells and smooth muscle cells and their changes in disease states were reviewed, especially the recent research progress of Kir channels in stem cells was introduced, in order to have a deeper understanding of Kir channels in vascular tissues and provide new ideas and directions for the treatment of related ion channel diseases

Depletion forces in colloidal system under geometrical confinements

The depletion interactions between two large spheres in a sea of small spheres under the symmetrical or unsymmetrical geometry confinements are studied through Monte Carlo simulations in this paper. The numerical results show that both the depletion potential and depletion force are affected due to the presence of the two plates

Fine-grained hardware switching scheme for power reduction in multiplication

© 2016 The Institution of Engineering and Technology. This Letter presents a fine-grained hardware switching scheme to choose from the proper hardware for low power computing. It exploits the word-length optimisation opportunities for multiplication unit. With the proposed technique, the gate-level simulation result on OpenRISC shows 23.7% power reduction for the multiplication unit, which accounts for 9.5% power reduction for its execution unit.status: publishe

Liquid Chromatography/Mass Spectrometry based serum metabolomics study on recurrent abortion women with antiphospholipid syndrome.

ObjectiveThe antiphospholipid syndrome (APS) is an important cause of acquired thromboembolic complications and pregnancy morbidity. The pathogenic mechanisms that damage the fetal-maternal unit and cause abnormal placental development are incompletely understood in APS patients. Liquid Chromatography/Mass Spectrometry (LC/MS) based metabolomics are applied for the mechanism of disease and further supporting the research of diagnosis and management in recent years. The aim of this research was to investigate the difference of serum metabolic profiles in recurrent abortion women with APS and healthy women to explore the mechanism of this disease.MethodsSerum samples of 25 recurrent abortion women with APS and 25 healthy women were collected and analyzed by LC/MS in this study. Potential biomarkers were discovered by multivariate statistical analysis and then identified based on analysis results.ResultsTotally, we identified five biomarkers that involved in different metabolic pathway such as purine metabolism, amino acid metabolism and tyrosine metabolism. These biomarkers showed different roles in disease development.ConclusionMetabolomics was proved as a powerful tool in understanding the mechanism of recurrent abortion caused by APS

On the General Mathematical Framework, Calibration/Compensation Method, and Applications of Non-Ideal Software Defined Harmonics Rejection Transceivers

© 2004-2012 IEEE. Recently harmonic interference rejection has been recognized as a crucial bottleneck of truly wide-band software defined radio transceivers. Phase and gain mismatches among mixing paths, typical for nanoscale technology nodes, severely impact the achievable rejection ratio in classical harmonic rejection transceivers. This paper proposes an alternative digital intensive architecture, which enables increased harmonic interference rejection for wide-band SDR transceivers impacted by severe gain and phase mismatches. A generic mathematical framework of the target architecture is introduced to support a systematic design space exploration for multi-path harmonic interference rejection transceivers. With the framework, an iterative on-die estimation and compensation of mismatch for both the transmitter and receiver are presented. Case study with four mixing paths shows that ideal rejection can be achieved when targeting a single dominating harmonic interferer, and joint suppression of the 3rd and 5th order harmonic interferers of at least 70 dB can be obtained under realistic radio input scenarios.status: publishe

Computation-skip error resilient scheme for recursive CORDIC

Aggressive voltage and frequency scaling are widely utilized to exploit the design margin introduced by the process, voltage and environment variations. However, scaling beyond the critical voltage or frequency results to numerous timing errors, and hence unacceptable output quality. In this paper, a computation-skip (CS) scheme is proposed for recursive digital signal processors with a fixed cycles per instruction (CPI) to correct timing errors. A CORDIC processor with the proposed CS scheme still functions when scaling beyond the sub-critical voltage or frequency. It improves EVM by 47.9 dB at its most critical frequency or supply voltage, and extends the voltage scaling limit by 90 mV w.r.t the conventional CORDIC. Besides, it is more than 1.7X energy efficient w.r.t. the conventional highspeed CORDIC, which is designed for a more aggressive scaling.status: publishe

Computation-skip Error Mitigation Scheme for Power Supply Voltage Scaling in Recursive Applications

© 2016, Springer Science+Business Media New York. Aggressive power supply voltage Vddscaling is widely utilized to exploit the design margin introduced by the process, voltage and environment variations. However, scaling beyond the critical Vddresults to numerous setup timing errors, and hence to an unacceptable output quality. In this paper, we propose computation-skip (CS) scheme to mitigate setup timing errors, for recursive digital signal processors with a fixed cycles per instruction (CPI). A coordinate rotation digital computer (CORDIC) with the proposed CS scheme still functions when scaling beyond the error-free voltage. It enables better-than-worst-case design constraint and achieves 1.82 X energy saving w.r.t. nominal Vddcondition, another 1.49 X energy saving without quality degradation, and another 1.09 X energy saving when sacrificing 8.35 dB output quality.status: publishe

An Automatic Defect Detection System for Petrochemical Pipeline Based on Cycle-GAN and YOLO v5

Defect detection of petrochemical pipelines is an important task for industrial production safety. At present, pipeline defect detection mainly relies on closed circuit television method (CCTV) to take video of the pipeline inner wall and then detect the defective area manually, so the detection is very time-consuming and has a high rate of false and missed detections. To solve the above issues, we proposed an automatic defect detection system for petrochemical pipeline based on Cycle-GAN and improved YOLO v5. Firstly, in order to create the pipeline defect dataset, the original pipeline videos need pre-processing, which includes frame extraction, unfolding, illumination balancing, and image stitching to create coherent and tiled pipeline inner wall images. Secondly, aiming at the problems of small amount of samples and the imbalance of defect and non-defect classes, a sample enhancement strategy based on Cycle-GAN is proposed to generate defect images and expand the data set. Finally, in order to detect defective areas on the pipeline and improve the detection accuracy, a robust defect detection model based on improved YOLO v5 and Transformer attention mechanism is proposed, with the average precision and recall as 93.10% and 90.96%, and the F1-score as 0.920 on the test set. The proposed system can provide reference for operators in pipeline health inspection, improving the efficiency and accuracy of detection